The present invention relates generally to analog-to-digital (A/D) converters and conversion techniques. More particularly, the present invention pertains to correction of nonlinearity and gain error in A/D converters and conversion techniques, e.g., pipelined A/D converters.
FIG. 1 illustrates a conventional pipelined A/D converter 10. The A/D converter 10 converts an analog electrical input signal Vin into a digital representation thereof Dout, e.g., analog samples of the input Vin are converted. Various illustrative exemplary n-bit A/D converters can be implemented. It should be understood that a resolution of any number of bits may be implemented uses a varied number of different stages 12 of the A/D converter 10. In other words, the resolution of an A/D converter can be referred to as an n-bit A/D converter, where n represents the number of digital output bits. The A/D converter 10 has the analog input signal Vin provided on an initial stage 16 of the plurality of stages 12. Each of the plurality of stages 12 of the A/D converter 10 converts a portion of the analog input Vin applied to input 14, and as such contributes to the digital output representation Dout.
The pipelined A/D converter 10 receives the analog input Vin at the first stage 16 for processing. The first stage determines one or more bits. A residue R0 representing the portion of the analog input Vin not converted by the initial stage 16 is generated and passed to a subsequent stage for processing to determine one or more digital bits. This process continues through each of the remaining stages 19 of the plurality of stages 12 which form part of the A/D converter 10. In other words, when a prior stage completes processing of an analog input or a residue applied thereto, it provides for an analog residue to be applied to a next subsequent stage for analog to digital conversion and for application of an analog residue to the next subsequent stage. The prior stage is then ready to receive a new analog input sample or residue to process. In other words, a pipeline is filled.
Due to the time required to fill the pipeline, pipelining causes an initial latency in computing the digital representation corresponding to an analog input sample. However, pipelining increases the rate at which digital representations corresponding to sequential analog input samples are generated by the converter due to the parallel processing of the sampled analog input signal.
As shown in FIG. 1, the pipelined A/D converter 10 includes M pipelined stages 12 and a digital error correction (DEC) circuit (e.g., a combining circuit) 18. The pipelined initial stage 16 receives the analog input signal Vin at input 14. The pipelined stages 12 produce respective analog outputs, e.g., analog outputs 20, 22, or, in other words, analog residues such as R0 from the first stage 16. The analog residues (e.g., R0) from respective pipelined stages 12 are respectively coupled to the analog inputs of subsequent pipelined stages. For example, analog residue R0 resulting from the initial stage 16 is coupled to stage 2 (one of blocks 19 of stages 12).
Generally, each stage includes similar elements. For example, as shown in FIG. 1, stage 2 (one of blocks 19 of the stages 12) includes a sample and hold circuit 30, an analog-to-digital converter (ADC) 32, a digital-to-analog converter (DAC) 34, and a summing circuit 36. The sample and hold circuit 30 receives the analog input signal 31 applied thereto (i.e., amplified analog residue R0) and holds the signal for later processing to generate the analog input of the next stage of the pipelined A/D converter 10 (i.e., stage 3).
The ADC 32 performs an analog-to-digital conversion of the input signal resulting in N bits 35 to be provided to DEC circuit 18. The N-bit digital output 35 of stage 2 is provided to DAC 34 for conversion to an analog signal 37 based thereon. The analog signal 37 is subtracted in summing circuit 36 from the held analog sample signal 39 to generate the analog residue 22 of stage 2. In other words, the difference between the analog input to ADC 32 and the DAC 34 analog output provides the residue 22. The residue 22 is amplified by an interstage amplifier 40 to provide an amplified residue 22 to be applied to stage 3. In the exemplary embodiment of stage 2, the amplification has a gain of 2N.
The digital outputs of each stage 12 (e.g., digital output 35 of stage 2) are input to DEC circuit 18. The DEC circuit 18 generates the digital output Dout of the A/D converter 10, i.e., a series of bits, based on the digital outputs from all the stages 12. For example, if the digital output includes DMxe2x88x921 to D0, and n=4 bits, then the digital output is D3, D2, D1, and D0, where D3 is the most significant bit (MSB) and D0 is the least significant bit (LSB). The DEC circuit 18 has, for example, a series of delays, or shift registers, to delay the digital output of each stage 12 so that the respective digital outputs for the same sampled signal can be combined.
Pipelined A/D converters are generally known and may be implemented in any number of ways. For further information regarding such conventional A/D converters, the following reference materials are provided: Stephen H. Lewis et al., xe2x80x9cA Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter,xe2x80x9d IEEE J. Solid-State Circuits, vol. Sc-22, no. 6, pages 954-961, Dec. 1987; Stephen H. Lewis et al., xe2x80x9cA 10-b 20-Msample/s Analog-to-Digital Converter,xe2x80x9d IEEE J. Solid-State Circuits, vol. 27, no. 3, pages 351-358, March 1992; Thomas B. Cho et al., xe2x80x9cA 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter,xe2x80x9d IEEE J. Solid-State Circuits, vol. 30, no. 3, pages 166-172, March 1995; Krishnaswamy Nagaraj et al., xe2x80x9cA 250-mW, 8-b, 52-Msample/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers,xe2x80x9d IEEE J. Solid-State Circuits, vol. 32, no. 3, pages 312-320, March 1997; and Yuh-Min Lin et al., xe2x80x9cA 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-xcexcm CMOS,xe2x80x9d IEEE J. Solid-State Circuits, vol. 26, no. 4, pages 628-636, April 1991, each of which are incorporated by reference in their entireties.
As is apparent, the pipelined A/D converter 10 includes analog portions and digital portions. For example, the DEC circuit 18 is a digital component portion, whereas the DAC 34, and interstage amplifier 40, are analog portions. In practice, every analog component in the pipelined A/D converter 10 exhibit non-ideal circuit behavior that will tend to degrade the overall conversion performance of the converter 10. For example, in typical switched capacitor implementations of DACs, noise or nonlinearity arises from the static capacitor mismatches employed in the digital-to-analog conversion performed thereby.
There is a speed/accuracy design tradeoff in the design of high-end pipelined A/D converters. Generally, the desired accuracy of a pipelined architecture is limited by nonlinearity, offset, and gain errors. For example, such errors may be introduced by the input sample and hold, the ADC of each stage, the DAC of each stage, and the interstage gain amplification of the analog residues provided by a stage to a subsequent stage. As indicated above, such various non-idealities in the A/D converter 10 result in errors, e.g., nonlinearity error, being present in the A/D converter transfer function and result in a corresponding reduction in performance of the A/D converter.
To meet the accuracy requirements as defined by the bits of A/D resolution, the nonlinearities must not exceed 1 least significant bit (LSB) in magnitude. Although the nonlinearities in a pipelined A/D converter may be less than 1 LSB, they may have a repetitive or periodic nature, which results in the generation of spurious tones in the frequency spectra of the digital representation of the analog input. An important measure of an A/D converter""s performance is spurious free dynamic range (SFDR), which is defined in the frequency domain as the amplitude difference between a spectrally pure input signal and the highest non-input signal component present in the frequency spectra of the A/D converter""s digital output representation Dout of the analog input signal Vin. Some of the non-idealities that affect the SFDR performance of the pipeline converters include, but clearly is not limited to, the amplification techniques, capacitor matching, and reference voltage variations.
SFDR is particularly important in a communication system. For example, A/D converter design for wideband receivers in a communication system are of significant importance. Such wideband receivers must be able to enable greater traffic density and flexibility and also handle multiple modulation standards. As a result of such requirements, most signal processing in the receiver design is performed in the digital domain and, as such, the A/D converter is used at the head end of the signal chain in such a receiver design. Therefore, A/D converter performance requirements, particularly for such communication system receiver designs, are significantly greater than for most other A/D converter designs. For example, at least with respect to a particular embodiment of receivers, A/D converters must be able to perform at high speed in the range of 50 to 65 MHz, and also have a resolution of at least 16 bits with an effective number of bits being in the range of 12.83 to 14.75 bits. Further, the SFDR should be in the range of 96 db to 115 db. Likewise, the design should always be kept to a minimum chip implementation area with cost considerations taken into consideration.
Pipelined A/D converters such as those described herein may be used for to such communication system applications. However, to meet the ever increased A/D converter requirements, the non-idealities present in pipelined A/D converters need to be addressed.
Various techniques attempt to address certain non-idealities of a pipelined A/D converter. For example, in U.S. Patent Application Publication 2002/0041248 A1 to Galton, entitled xe2x80x9cDigital Cancellation of D/A Converter Noise in Pipelined A/D Converters,xe2x80x9d published 11 Apr. 2002, a digital noise cancellation logic circuit that measures and cancels the A/D conversion error caused by DAC noise is presented for a switched capacitor based pipelined A/D converter. Galton alleges to provide a technique for digital cancellation of DAC noise arising from static analog errors such as capacitor mismatches. Further, for example, in an article by E. J. Siragusa and I. Galton, entitled xe2x80x9cGain error correction technique for pipelined analogue-to-digital converters,xe2x80x9d Electronic Letters, vol. 36, no. 7, Mar. 2000, a gain error correction technique is presented that measures and digitally compensates for analog gain errors present in each stage of a pipelined A/D converter.
Although various techniques have been provided to attempt to separately address nonlinearity and gain error for pipelined A/D converters, there is further need for techniques to improve analog to digital conversion performance, e.g., SFDR.
The present invention provides correction for non-linearity and gain error in A/D converters and conversion techniques.
A method of correcting error in a multiple stage analog to digital converter over a plurality of clock cycles (e.g., a plurality of clock cycles preceded by a plurality of initial startup cycles) according to the present invention includes providing a digital signal from a first stage of the multiple stage analog to digital converter based on an input signal to the first stage of the multiple stage analog to digital converter. An analog signal is provided from the first stage of the multiple stage analog to digital converter based on the first stage digital signal. The analog signal provided by the first stage of the multiple stage analog to digital converter is subtracted from the input signal resulting in a first stage analog residue signal. The resultant first stage analog residue signal is amplified and the amplified first stage analog residue signal is applied to a second stage of one or more subsequent stages of the multiple stage analog to digital converter. A first stage digital residue signal is provided from the one or more subsequent stages based on the amplified first stage analog residue signal applied thereto. Continuously, over the plurality of clock cycles, averaging the first stage digital residue signal with a pseudorandom sequence results in an averaged first stage digital residue correction signal. The averaged first stage digital residue correction signal is subtracted from a sum of the first stage digital residue signal and the first stage digital signal of the multiple stage analog to digital converter for use in providing a non-linearity corrected digital output signal. Also, continuously, over the plurality of clock cycles, the non-linearity corrected digital output signal is averaged to correct for gain error.
In one embodiment of the method, subtracting the averaged first stage digital residue correction signal from a sum of the first stage digital residue signal and the first stage digital signal of the multiple stage analog to digital converter to provide a non-linearity corrected digital output signal includes subtracting the averaged first stage digital residue correction signal from the first stage digital residue signal resulting in a corrected first stage digital residue signal. The corrected first stage digital residue signal is summed with the first stage digital signal resulting in the non-linearity corrected output signal.
In another embodiment of the method, the method further includes providing and subtracting additional averaged digital residue correction signals associated with additional stages of the one or more subsequent stages to correct for non-linearity.
In another embodiment of the method, the method includes correcting alignment of the first stage digital residue signal and the digital signal from the first stage of the multiple stage analog to digital converter (e.g., using DEC logic).
Yet further, in another embodiment, averaging the first stage digital residue signal with a pseudorandom sequence resulting in an averaged first stage digital residue correction signal includes averaging the first stage digital residue signal with a pseudorandom sequence that is based on a pseudorandom sequence used to provide the analog signal from the first stage of the multiple stage analog to digital converter based on the digital signal.
Preferably, according to the present invention, providing the digital signal from the first stage of the multiple stage analog to digital converter based on the input signal to the first stage includes providing an N-bit digital signal from the first stage of the multiple stage analog to digital converter based on the input signal thereto; N is an integer in the range of 3 to 6.
Another method of correcting non-linearity error and gain error in a multiple stage pipeline analog to digital converter according to the present invention is described. The method includes using an analog to digital conversion to provide a digital signal from a first stage of the multiple stage pipeline analog to digital converter based on an input signal to the first stage thereof and using a digital to analog conversion to provide an analog signal from the first stage of the multiple stage pipeline analog to digital converter based on the first stage digital signal provided by the analog to digital conversion. The digital to analog conversion introduces non-linearity error into the multiple stage pipeline analog to digital converter. The analog signal provided by the digital to analog conversion is subtracted from the input signal resulting in a first stage analog residue signal. The resultant first stage analog residue signal is amplified and the amplified first stage analog residue signal is applied to one or more subsequent stages of the multiple stage pipeline analog to digital converter. The amplification introduces gain error into the multiple stage pipeline analog to digital converter. At least an analog to digital conversion is used to provide a first stage digital residue signal from the one or more subsequent stages based on the amplified first stage analog residue signal. A digital output is provided during each clock cycle of a clock time period based on at least the first stage digital signal provided by the analog to digital conversion in the first stage and the first stage digital residue signal. Providing the digital output includes correcting, during each clock cycle of a plurality of clock cycles of the clock time period, at least a portion of the non-linearity error with use of an averaging over time of the first stage digital residue signal with a pseudorandom sequence, wherein such correction is used to provide a non-linearity corrected digital signal. Further, providing the digital output includes correcting, during the each clock cycle of a plurality of clock cycles of the clock time period, at least a portion of the gain error by averaging the non-linearity corrected digital signal over time.
In one embodiment of the method, correcting at least a portion of the non-linearity error includes averaging the first stage digital residue signal with a pseudorandom sequence resulting in an averaged first stage digital residue correction signal, subtracting the averaged first stage digital residue correction signal from the first stage digital residue signal resulting in a corrected first stage digital residue signal, and summing the corrected first stage digital residue signal with the first stage digital signal for use in providing the non-linearity corrected digital signal.
In another embodiment, averaging over time of the first stage digital residue signal with a pseudorandom sequence includes averaging the first stage digital residue signal with a pseudorandom sequence that is based on a pseudorandom sequence used to perform the digital to analog conversion.
Further, another method of correcting non-linearity error and gain error in a multiple stage pipeline analog to digital converter over a plurality of clock cycles is described. The method includes correcting, during each of the plurality of clock cycles, at least a portion of non-linearity error introduced by a digital to analog conversion performed in a first stage of the multiple stage pipeline analog to digital converter with use of an averaging over time of a first stage digital residue signal provided by the remainder stages of the multiple stage pipeline analog to digital converter. Such correction is used to provide a non-linearity corrected digital signal. The method further includes correcting, during each of the plurality of clock cycles, at least a portion of a gain error introduced by one or more amplifiers in the multiple stage pipeline analog to digital converter by averaging the non-linearity corrected digital signal over time.
In one embodiment, averaging over time of the first stage digital residue signal includes averaging the first stage digital residue signal with a pseudorandom sequence that is based on a pseudorandom sequence used to perform the digital to analog conversion.
A multiple stage pipeline analog to digital converter apparatus is also provided. The apparatus includes a plurality of stages including a first stage and one or more subsequent stages. At least the first stage is configured to receive an input signal and is connected to a subsequent stage by an amplifier. The first stage includes an analog to digital converter (e.g., an N-bit analog to digital converter, where N is an integer in the range of 3 to 6) configured to receive the input signal and convert the input signal into a digital signal, a digital to analog converter configured to receive the digital signal from the analog to digital converter and convert the digital signal to an analog signal, and a subtraction circuit operable to subtract the analog signal received from the digital to analog converter from the input signal applied to the first stage resulting in a first stage analog residue signal that is applied to the amplifier between the first stage and the one or more subsequent stages. The one or more subsequent stages include at least one stage operable to convert the first stage analog residue signal to a first stage digital residue signal. The apparatus further includes a non-linearity correction circuit associated with the first stage operable to continuously provide, during each of a plurality of clock cycles, an average of the first stage digital residue signal with a pseudorandom sequence resulting in an averaged first stage digital residue correction signal.
Further, the apparatus includes a combining circuit configured to subtract the averaged first stage digital residue correction signal from a sum of the first stage digital signal provided by the analog to digital converter and at least the first stage digital residue signal for use in providing a non-linearity corrected digital output signal. In addition, the apparatus includes a gain correction circuit operable to continuously provide, during each of the plurality of clock cycles, an average of the non-linearity corrected digital output signal.
In one embodiment of the apparatus, the logic circuit is configured to subtract the averaged first stage digital residue correction signal from the first stage digital residue signal resulting in a corrected first stage digital residue signal and, thereafter, sum the corrected first stage digital residue signal with the first stage digital signal for use in providing the non-linearity corrected digital output signal.
In another embodiment of the apparatus, at least one additional stage of the one or more subsequent stages includes an additional non-linearity correction circuit associated with the additional stage operable to average an additional stage digital residue signal with a pseudorandom sequence resulting in an additional stage averaged correction signal. A combining circuit is further configured to subtract the additional stage averaged correction signal from the sum of the first stage digital signal and at least the first stage digital residue signal for use in providing the non-linearity corrected digital output signal.
In yet another embodiment, the combining circuit includes digital correction circuitry configured to align at least the first stage digital residue signal provided by the one or more subsequent stages of the multiple stage pipeline analog to digital converter apparatus.
Yet further, in another embodiment, the digital to analog converter of the first stage has an associated pseudo-random sequence associated therewith. The pseudorandom sequence used by the non-linearity correction circuit is a pseudorandom sequence based on the pseudorandom sequence associated with the digital to analog converter.
The methods and apparatus described herein may be advantageously used as part of a communication system, e.g., a base station of a communication system.